The present invention is related to the field of digital to analog converters, in one embodiment, for optical computing.
Optical computing offers advantages over electronic computing for many applications. PCT publications WO 00/72104 and WO 00/72107 describe an optical analog computer which calculates general linear transforms using massively parallel processing. Applications include image compression, image enhancement, pattern recognition, signal identification, signal compression, optical interconnects and crossbar systems, morphologic operations, logical operations, image and signal transformation and modeling neural networks. While it may sometimes be possible, for example in image compression, to use input data that is initially in analog optical form, for many applications the input data is initially stored electronically in digital form, and must be converted into analog optical form before feeding it into the optical computer. To take advantage of the high computation speed of a massively parallel optical computer, there is a need for a system which rapidly converts a large amount of digital data into analog form.
Digital to analog converters (DAC) and analog to digital converters (ADC) are well known. An array of values can be converted from digital to analog form, or from analog to digital form, either in series, feeding each value into a single converter, or in parallel, simultaneously feeding all the values in the array into separate converters. For a very large array, serial conversion can be very slow, and parallel conversion can be very expensive since it requires a large number of converters.
Kleinfelder et al., xe2x80x9cA 10 kframe/s 0.18 xcexcm CMOS Digital Pixel Sensor with Pixel-Level Memory,xe2x80x9d 2001 IEEE International Solid-State Circuits Conference, Feb. 5-7, 2001, Session 6.1, CMOS Image Sensors with Embedded Processors, pages 68, 69 and 435, describe a system for parallel analog to digital conversion for a large array of pixels, in which the circuitry needed for each pixel is simpler and less expensive than a complete stand-alone analog to digital converter. A digital ramp signal, consisting of a sequence of 8-bit numbers in numerical order, is generated centrally, together with an analog ramp signal equivalent to the digital ramp signal, i.e. a triangle wave. Both signals are fed to all the pixels. Each pixel has a comparator circuit which compares the analog ramp signal to the value of the analog input for that pixel. When the ramp signal first exceeds the value of the analog input, the comparator circuit activates a digital latching circuit, which latches the current value of the digital ramp signal into the digital memory of that pixel. This digital memory serves as the digital output for the analog to digital conversion.
Albu et al., U.S. Pat. No. 6,320,565, describes a system for digital to analog conversion of a large array of pixels for driving an electro-optic display device, in which all the pixels in one row of the array are converted in parallel, followed by the next row, and continuing until the entire array is converted, then beginning a new frame. A global ramp generator generates an analog ramp signal going from zero to a maximum voltage, which is applied to capacitors associated with all the pixels in the row being processed at that time. An analog to digital converter produces a corresponding global digital ramp signal. For each column in the array, there is a digital comparator which compares the digital ramp signal to an incoming digital video signal for the pixel at the intersection of that column and the row being processed. When the digital ramp signal matches the digital input signal for that column, a sample and hold circuit opens, and isolates the analog ramp signal from the capacitor associated with that pixel, and the voltage on that pixel then remains fixed, decaying slowly until the next frame is processed. In the next ramp cycle, the analog ramp signal is applied to the capacitors associated with the pixels in the next row, and so on. Several ramp cycles before a given row is processed, the analog ramp signal is temporarily reconnected to the capacitors of that row at a time when the analog ramp is close to zero, resetting those pixels to zero. This prevents image artifacts that would occur due to the residual state of the electro-optic material from previous frames.
An aspect of some embodiments of the invention concerns an array of circuitry for digital to analog conversion in parallel, in which signals for all the pixels of a two-dimensional array of pixels are converted simultaneously, rather than processing only one row of pixels at a time, as in Albu et al. Although this may require more complicated circuitry than Albu et al., for example possibly including a separate digital comparator for each pixel rather only one per column, it is possible to display a frame much more quickly than in the system disclosed by Albu et al. and the circuitry is still simpler and less expensive than a prior art array of circuitry with a stand alone digital to analog converter for each pixel. For the video display application of Albu et al., there would be no advantage to converting all of the pixels of a frame into analog form in parallel, since it is never necessary to display more than a few tens of frame per second, and converting all of the pixels in a frame in parallel would require more expensive hardware than only converting all of the pixels in a row in parallel Even if only one row in the image is updated at a time, at tens of frames per second, it will appear to the human eye as if the entire image is changing continuously. For optical computing, however, it may be useful to convert thousands of frames per second from digital to analog form, for example to avoid having the processor remain idle for a large fraction of the time while the pixels are updated. Thus, for optical computing the cost of the additional hardware may be justified.
The circuitry in accordance with some embodiments of the invention accomplishes the reverse of the task accomplished by the analog to digital conversion array described by Kleinfelder et al. In an exemplary embodiment of the invention, there arc a digital ramp signal and an equivalent analog ramp signal, which are optionally generated centrally, and are accessible to some or all of the elements of the array. In some embodiments of the invention, each element of the array comprises a digital comparator, which compares the digital ramp signal to the input value held in a digital memory associated with that element. When the two values are equal, the comparator generates an enabling signal which activates a sampling and holding circuit associated with that element. The sampling and holding circuit samples the value of the analog ramp signal at that time, and sets the value of an analog output for that element to the value of the analog ramp signal. The analog output is held at this value until the next time the comparator sends the enabling signal to the sampling and holding circuit. The sampling and holding circuit can be quite simple, optionally comprising only a transistor and a capacitor.
Optionally, the output of each pixel in the DAC array is connected directly to the corresponding input pixel of the optical computer, rather than transferring the optical signals along optical fibers. Optionally, the input pixels of the optical computer comprise a multi-quantum well structures made of alternating layers of gallium arsenide (GaAs) and gallium aluminum arsenide (GaAlAs), and the input pixels of the optical computer are bonded to the output pixels of the DAC array using the Flip Chip Bonding technique. Optionally, the DAC array is a monolithic silicon integrated circuit, whose elements are arranged with the same spacing as the input pixels of the optical computer. Unlike in a conventional TV display, the updating of the input pixels need not be done at regular intervals, but optionally is done only when the optical computer requires the next set of input data. Optionally, only some of the elements are updated, when only partial updating is required. Optionally, some or all of the elements include a calibration circuit, for example a capacitor, to allow adjustment in the analog response of the element, for example to correct for physical defects and/or variability. Other types of technologies, for example semi-conductor technologies may be used instead of MQW technology.
An aspect of some embodiments of the invention concerns an array of circuitry for digital to analog conversion in parallel, in which there are two or more digital memory registers associated with each pixel, and a central controller (or, in some embodiments an element controller) can choose which set of digital memory registers to convert to analog voltages and load into the pixels. For example, while the first memory register in each pixel is being converted to analog form, new digital values could be loaded into the second memory register in each pixel. Or, several memory registers can be loaded into the pixels in rapid succession, one frame after the other, to do an optical computation, in less time than it takes to load that many frames into the digital memory registers. The values may be repeatedly cycled, as needed for specific computations, for example the coefficients of Digital Fourier Transform (DFT), a matrix and its transpose, real and imaginary parts. Alternatively, mathematical processing can be done electronically (in parallel) on the different memory registers, for example, for pre-processing of the input data to an optical computer, or for image enhancement if the array is used to drive a video display panel. For example, two or more frames could be averaged to reduce noise, or the difference between two frames could be taken to detect motion or other changes, or pixels from one frame could be substituted for pixels from another frame when the latter have a certain range of values. Optionally, the circuitry includes the ability to shift analog values in a row and/or a column in one or both directions.
Alternatively or additionally, to a digital memory, an element may include one or more analog memories that can be switched and used to drive the array and optionally loaded using said digital memory.
There is thus provided in accordance with an exemplary embodiment of the invention, a digital to analog converter array comprising:
a plurality of pixels arranged in an array and independently addressable to selectively modulate light;
a digital counter which generates a sequence of numbers in digital form;
an analog signal source which generates an analog signal that corresponds the sequence generated by the digital counter; and
a plurality of array elements which control the pixels, each element comprising:
a digital memory register holding at least one input number;
a comparator which generates an enabling signal responsive to a comparison between the number in the sequence and the input number; and
a sample and hold circuit which samples the value of the analog signal, responsive to said enabling signal, and sets an output voltage controlling a pixel to said value,
wherein the array is configured so that the comparators in all the array elements compare the number in the sequence to the input numbers held in said array elements substantially simultaneously.
Optionally, for at least one array element the output voltage controls the amount of light transmitted through the pixel controlled by said array element. Alternatively or additionally, for at least one array element the output voltage controls the amount of light reflected by the pixel controlled by said array element. Optionally, the pixel comprises a polarization rotating material controlled by the output voltage, and a polarizing filter. Alternatively or additionally, the pixel comprises a Multi Quantum Well structure, the reflectance of which controlled by the output voltage.
In an exemplary embodiment of the invention, for at least one array element the output voltage controls the amount of light emitted by the pixel controlled by said array element.
In an exemplary embodiment of the invention, said analog signal source comprises digital to analog converter which generates the analog signal by converting the sequence of numbers to said analog signal.
In an exemplary embodiment of the invention, said analog signal source comprises an analog circuit, which generates said analog signal. Optionally, the digital counter comprises an analog to digital converter which generates the sequence of numbers by converting the analog signal to said sequence of numbers.
In an exemplary embodiment of the invention, the sequence of numbers is in increasing numerical order, and the sequence repeats, starting from a smallest number, after reaching a largest number.
In an exemplary embodiment of the invention, the sequence of numbers is in decreasing numerical order, and the sequence repeats, starting from a largest number, after reaching a smallest number.
In an exemplary embodiment of the invention, the sequence of numbers alternately goes in increasing numerical order from a smallest number to a largest number, and in decreasing numerical order from the largest number to the smallest number.
In an exemplary embodiment of the invention, the sample and hold circuit comprises a capacitor, and the output voltage is substantially proportional to the charge on the capacitor. Optionally, the sample and hold circuit comprises a transistor whose gate is connected to the enabling signal, and whose base-to-collector impedance is decreased when the comparator generates the enabling signal, allowing the analog signal to charge up the capacitor to a voltage substantially dependent on the analog signal.
In an exemplary embodiment of the invention, said digital memory comprises a plurality of digital memory registers associated with each array element. Optionally, the array comprises a controller which controls which memory register the comparator reads the input number from in each array element. Optionally, the array includes a bus for writing to each register, wherein the controller is configured so that the comparator reads the input number from any one of the registers while the bus writes a next input number to another one of the registers. Optionally, the bus writes to each register using a daisy chain configuration.
In an exemplary embodiment of the invention, the controller is configured so that the comparator reads the input number from a same corresponding memory register in each array element. Optionally, the array includes a processing unit in each array element, which processing units are configured to read from and write to corresponding memory elements, and perform calculations, in each array clement in parallel, responsive to instructions from the controller. Optionally, the input number read by the comparator in each array element corresponds to the brightness of a location in a digital image, and the processors are used to perform image processing calculations.
In an exemplary embodiment of the invention, the digital counter is controllable to generate a different sequence of numbers depending on the number of bits in the input number.
In an exemplary embodiment of the invention, the numbers in the sequence have more bits than the input number. Optionally, the comparator does not use all of the bits in the numbers in the sequence when comparing them to the input number.
In an exemplary embodiment of the invention, the digital counter is controllable to be reset to a given number in the sequence. Optionally, the digital counter is reset when the comparator reads a new input number from the digital memory.
In an exemplary embodiment of the invention, the digital counter generates the numbers in the sequence at regular intervals of time. Optionally, the digital counter is configured so that said intervals are adjustable.
In an exemplary embodiment of the invention, the array includes an element selector which is configured to select one of the elements of the array, and to read the voltage at one or more locations in the circuitry of said element.
In an exemplary embodiment of the invention, at least some of the pixels in said array are selectable to be operated separately form other ones of said pixels.
In an exemplary embodiment of the invention, said array is fabricated as an integrated circuit.
In an exemplary embodiment of the invention, said array is integrated with an optical computer for which said array comprises a matrix for vector matrix multiplication.
In an exemplary embodiment of the invention, said digital memory register is selectably partitionable into multiple registers. Optionally, said register is partitionable into at least two registers. Alternatively or additionally, said register is partitionable into at least three registers.